1. Field of the Invention
The present invention relates to a pattern matching method for matching input information such as circuit connection information and the like with predetermined patterns which have already been prepared and registered, a timing analysis method for performing the timing analysis of semiconductor integrated circuits by using the pattern matching method, and a timing analysis device for executing the timing analysis method.
2. Description of the Related Art
In general, the functions of a semiconductor integrated circuit to be designed are divided into a hierarchical structure having a plurality of hierarchical phases and the design for the semiconductor integrated circuit is executed in each hierarchical phase in circuit design because it is difficult to execute a detailed design of the entire circuit simultaneously. This design method is called to as a hierarchical design method.
FIG. 1 is a diagram showing a microprocessor chip which is designed in a hierarchical structure having a plurality of functional blocks.
As shown in FIG. 1, the microprocessor chip is usually divided into several blocks B1 to B5. In FIG. 1, reference number 1000 designates the microprocessor chip as a semiconductor chip, the reference characters B1 to B5 indicate functional blocks such as a central processing unit (CPU) core block, a control logic block, a ROM, a RAM, and a cache memory.
The hierarchical design of the microprocessor is a method in which these functional blocks B1 to B5 are further divided into small-sized blocks. Finally, the hierarchical design of the microprocessor will reach a transistor design level in which each of transistors is designed. Usually, the hierarchical design of the microprocessor is completed when it reaches a design level where several gates that can be provided by a logical library are designed.
In the hierarchical design of the microprocessor, for example, the design in a chip level, where the plurality of blocks B1 to B5 are included, is executed after the functional block design level (Bottom up design method). Then, the design is executed every hierarchical layer by using software as a simulator.
In addition, the simulation of a timing design for delay will be performed (timing analysis) after the completion of the placement of the blocks and the wiring design process. A timing analysis program is used during this timing analysis process. For example, the longest bus (called to as a critical path) in each block is detected (path analysis) in order to check the timing against the delay including a wiring delay. During this timing analysis, in general, the timing analysis in the chip level is performed after the completion of the timing analysis for the block level.
FIG. 2 is a flow chart showing the process of the path analysis by using a conventional timing analysis.
First, data items of circuit connection information (net lists) are read and stored into a main memory in a simulator (Step S51) in advance.
Following this process, the direction of a signal propagation or a signal transfer of each transistor in the net list is determined (Step S52). Then, the circuit is divided into a plurality of blocks B1, . . . , Bn (Step S53).
The critical path in each block is determined (Steps S54 and S55). Then, the critical paths N (N is a positive integer) in the whole blocks designated by a user are reported to the user (Step S56).
The user refers to the result of the path analysis in order to decide a timing validity of the designed circuit. However, the conventional timing analysis method has the following drawback.
There is a case in which a net list is matched well in the level of the entire semiconductor chip, but it is not matched in a block level. For example, elements in a composition indicating one function are belonged to different blocks. In this case, it is difficult to perform the path analysis process properly.
FIG. 3 is a diagram showing a semiconductor integrated circuit chip including pre-charge bus circuits. FIG. 3 shows a specific example in which the drawback described above is present. In FIG. 3, P-channel MOS transistors 111 to 114 (hereinafter referred to as P-MOS transistors) are formed in the block B1. In the block B2, the N-channel MOS transistors (hereinafter referred to as N-MOS transistors) 121, 122, 123, 124, 125, 126, 127, and 128 are formed. The P-MOS transistor 111 and the N-MOS transistors 121 and 122 are connected in series between the power source VDD and the ground source VSS. Similarly, the P-MOS transistor 112 and the N-MOS transistors 123 and 124 are connected in series between the power source VDD and the ground source VSS, the P-MOS transistor 113 and the N-MOS transistors 125 and 126 are connected in series between the power source VDD and the ground source VSS, and the P-MOS transistor 114 and the N-MOS transistors 127 and 128 are also connected in series between the power source VDD and the ground source VSS.
For example, a clock signal .phi. is provided to both the gates of the P-MOS transistor 111 and the N-MOS transistor 121. That is, both gates of the P-MOS transistor 111 and the N-MOS transistor 121 receive the in-phase clock signal .phi.. The data item D1 is provided to the N-MOS transistor 122, and a bus signal wire 131 is connected to an output node that is connected between the P-MOS transistor 111 and the N-MOS transistor 121. Thus, the set of these components described above forms the function of a circuit.
Similarly, the set of P-MOS transistor 112, the N-MOS transistor 123, N-MOS transistor 124, and the bus wiring 132 forms the function of a circuit. The set of P-MOS transistor 113, the N-MOS transistor 125, N-MOS transistor 126, and the bus wiring 133 forms the function of a circuit. The set of P-MOS transistor 114, the N-MOS transistor 127, N-MOS transistor 128, and the bus wiring 134 forms the function of a circuit.
However, in the case of this circuit described above, the block B1 (for example, such as the CPU core)includes the P-MOS transistors 111 to 114 and the block B2 (for example, such as the control logic) includes N-MOS transistors 121 to 128. In this case, it is difficult to perform a timing analysis for the block B2 because a pair of the pre-charge buses (including the P-MOS transistor 111, the N-MOS transistor 121, the N-MOS transistor 1222, and the bus signal wire 131) is not grouped into one net list.
Thus, it is difficult to execute the timing analysis for a block having imperfect net list. In the prior art, this problem is solved manually by designers. However, the manual operation will cause mistakes and requires more operation time. Therefore the manual operation is not practical.
As described above, it is difficult to perform the timing analysis of a functional circuit in the block level by using the conventional timing analysis when elements in the functional circuit include different blocks even if the elements form the functional circuit such as the pre-charge bus circuit described above.